LATEST MODELS

Typical SPICE model files for each future generation are available here.

Attention: By using a PTM file, you agree to acknowledge both the URL of PTM: http://ptm.asu.edu/and the related publicationsin all documents and publications involving its usage.

P-MOSFET; Switch; Source Follower; Current Source; Current Ramp; Current Mirror; Common-Source Amplifier; CMOS Inverter; CMOS Inverter (w/capacitance) CMOS Inverter (slow transition) CMOS Transmission Gate; CMOS Multiplexer; Sample-and-Hold; Delayed Buffer; Leading-Edge Detector; Switchable Filter; Voltage Inverter; Inverter Amplifier; Inverter.

New!

Starting with the fundamentals of CMOS scaling to nanometer dimensions, various advanced device and circuit concepts, including RF CMOS, low power CMOS, silicon memory, silicon-on-insulator, SiGe bipolar, strained silicon MOSFET’s, etc. Silicon carbide - The latest breakthrough in high-voltage switching and rectification. ST’s portfolio of silicon carbide devices incluses STPOWER SiC MOSFETs ranging from 650 to 1700 V with the industry’s highest junction temperature rating of 200 °C for more efficient and simplified designs, and STPOWER SiC diodes ranging from 600 to 1200 V which feature negligible switching losses.

Mosfet device overview: Here, we first discuss the basic structure, operation and important terms related to the core unit of CMOS i.e. MOSFET or simply MOS. The first successful MOS transistor would use metals for the gate material, SiO2 (oxide) for insulator and semiconductor for substrate. MOSFET is a specific type of Field Effect Transistor - Metal Oxide Semiconductor Field Effect Transistor. (Other typers could be JFET, ISFET, MESFET etc.) CMOS stands for Complementary Metal Oxide Semiconductor, relies on a p channel and a N channel device on the same substrate. It lies at the heart of modern electronics.

June 01, 2012:

PTM releases a new set of models for multi-gate transistors (PTM-MG), for both HP and LSTP applications. It is based on BSIM-CMG, a dedicated model for multi-gate devices.

Acknowledgement: PTM-MG is developed in collaboration with ARM.

Please start from models and param.inc.

• 7nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
• 10nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
• 14nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
• 16nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS
• 20nm PTM-MG HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS

The entire package is also available here: PTM-MG

November 15, 2008:

PTM releases a new set of models for low-power applications (PTM LP), incorporating high-k/metal gate and stress effect.

• 16nm PTM LP model: V2.1
• 22nm PTM LP model: V2.1
• 32nm PTM LP model: V2.1
• 45nm PTM LP model: V2.1

September 30, 2008:

PTM releases a new set of models for high-performance applications (PTM HP), incorporating high-k/metal gate and stress effect.

• 16nm PTM HP model: V2.1
• 22nm PTM HP model: V2.1
• 32nm PTM HP model: V2.1
• 45nm PTM HP model: V2.1

February 29, 2008:

Cmos Basics

PTM releases the model for metallic carbon nanotube (CNT-interconnect).

• Verilog-A based model card for CNT-interconnect is available at post-si

October 29, 2007:

Cmos Vs Mosfet

PTM releases a new version for sub-45nm bulk CMOS, providing new modeling features of metal gate/high-k, gate leakage, temperature effect, and body bias.

• 22nm PTM model for metal gate/high-k CMOS: V2.0
• 32nm PTM model for metal gate/high-k CMOS: V2.0
• 45nm PTM model for metal gate/high-k CMOS: V2.0

July 30, 2007

PTM extends the effort to post-Si devices. The first release is for carbon nanotube FET (CNT-FET).

• Verilog-A based model card for CNT-FET is available at post-si

December 15, 2006

PTM for bulk CMOS is released, for 22nm node.

• 22nm BSIM4 model card for bulk CMOS: V1.0

February 22, 2006

A new generation of PTM for bulk CMOS is released, for 130nm to 32nm nodes. It captures the latest technology advances and achieves better scalability and continuity across technology nodes.

• 32nm BSIM4 model card for bulk CMOS: V1.0
• 45nm BSIM4 model card for bulk CMOS: V1.0
• 65nm BSIM4 model card for bulk CMOS: V1.0
• 90nm BSIM4 model card for bulk CMOS: V1.0
• 130nm BSIM4 model card for bulk CMOS: V1.0

September 30, 2005

• 32nm BSIM4 model card for bulk CMOS: V0.0
• 32nm sub-circuit model for FinFET (double-gate): V0.0
• 45nm sub-circuit model for FinFET (double-gate): V0.0 [for better convergence in the simulation, you can initialize the node voltage when using PTM for FinFET]

July 31, 2002

• 45nm BSIM4 model card for bulk CMOS: V0.0
• 65nm BSIM4 model card for bulk CMOS: V0.0

May 31, 2001

• 90nm BSIM3 model card for bulk CMOS: V0.0
• 130nm BSIM3 model card for bulk CMOS: V0.0
• 180nm BSIM3 model card for bulk CMOS: V0.0

Mosfet Cmos Advantages

References

Cmos Mosfet

• S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, 'Exploring sub-20nm FinFET design with predictive technology models,' to be published at DAC, 2012.
• A. Balijepalli, S. Sinha, Y. Cao, 'Compact modeling of carbon nanotube transistor for early stage process-design exploration,' ISLPED, pp. 2-7, 2007.
• W. Zhao, Y. Cao, 'New generation of Predictive Technology Model for sub-45nm early design exploration,' IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
• Y. Cao, T. Sato, D. Sylvester, M. Orshansky, C. Hu, 'New paradigm of predictive MOSFET and interconnect modeling for early circuit design,' pp. 201-204, CICC, 2000.